Channel Segmentation Design for Symmentrical FPGAs
نویسندگان
چکیده
| The channel segmentation design problem for symmetrical FPGAs is the problem of designing segmented tracks in the interconnection channels to provide good net routability and delay performance at the same time. In this paper, we show how to decompose the problem into the segmentation design problems of the vertical and horizontal channels by a statistical analysis of the net distribution on a symmetrical FPGA. And we propose an eeective approach for segmented channel design when the allowed number of tracks in a channel is xed and limited.
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